At the center of CS-4 is the newly announced WSE-3 Turbo — like the WSE-3,
the largest AI processor ever built. One wafer integrates
4 trillion transistors and 900,000 AI-optimized cores across
46,225 mm² of silicon, with 44 GB of SRAM directly on the wafer.1
The Turbo doubles what matters: AI compute to 250 PFLOPS per wafer, memory bandwidth
to 43.2 PB/s, on-chip fabric bandwidth to 53.5 PB/s, and off-chip
I/O to 2.4 Tb/s. Because memory bandwidth determines decode speed and
throughput, this is a step-change in both.1
Why wafer scale? A single wafer holds the model weights and the entire interconnect on-chip,
so inference never bottlenecks on GPU-to-GPU links. Compared with NVIDIA's flagship B200, one
WSE-3 carries 19× more transistors and delivers 28× more AI compute —
and it does the work that would otherwise require racks of GPUs.4